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photodiode arrays with ampli er photodiode array combined with signal processing ic for x-ray detection s8865-64g/-128g/-256g s8866-64g-02/-128g-02 www.hamamatsu.com 1 structure parameter symbol * 1 s8865-64g s8865-128g s8865-256g s8866-64g-02 s8866-128g-02 unit element pitch p 0.8 0.4 0.2 1.6 0.8 mm element diffusion width w 0.7 0.3 0.1 1.5 0.7 mm element height h 0.8 0.6 0.3 1.6 0.8 mm number of elements - 64 128 256 64 128 - effective photosensitive area length - 51.2 51.2 51.2 102.4 102.4 mm board material - glass epoxy - * 1: refer to following gure. enlarged drawing of photosensitive area kmpdc0072ea the s8866-64g-02/-128g-02 are photodiode arrays with an ampli er and a phosphor sheet attached to the photosensitive area for x-ray detection. the signal processing circuit chip is formed by cmos process and incorporates a timing generator, shift register, charge ampli er array, clamp circuit and hold circuit, making the external circuit con guration simple. a long, narrow image sensor can be con gured by arranging multiple arrays in a row. as the dedicated driver circuit, the c9118 series (sold separately) is provided. (not compatible with the s8865-256g and s8866-64g-02. ) features applications large element pitch: 5 types available s8865-64g: 0.8 mm pitch 64 ch s8865-128g: 0.4 mm pitch 128 ch s8865-256g: 0.2 mm pitch 256 ch s8866-64g-02: 1.6 mm pitch 64 ch s8866-128g-02: 0.8 mm pitch 128 ch 5 v power supply operation detectable energy range: 30 k to 100 kev simultaneous integration by using a charge ampli er array sequential readout with a shift register (data rate: 500 khz max.) low dark current due to zero-bias photodiode operation integrated clamp circuit allows low noise and wide dynamic range integrated timing generator allows operation at two different pulse timings line sensors for x-ray detection
photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 2 absolute maximum ratings parameter symbol value unit supply voltage vdd -0.3 to +6 v r ef erence voltage vref -0.3 to +6 v photodiode voltage vpd -0.3 to +6 v gain selection terminal voltage vgain -0.3 to +6 v master/slave selection voltage vms -0.3 to +6 v clock pulse voltage v (clk) -0.3 to +6 v reset pulse voltage v (reset) -0.3 to +6 v external start pulse voltage v (extsp) -0.3 to +6 v operating temperature * 2 topr -5 to +60 c storage temperature * 2 tstg -10 to +70 c * 2: no condensation recommended terminal voltage electrical characteristics [ta=25 c, vdd=5 v, v(clk)=v(reset)=5 v] parameter symbol min. typ. max. unit supply voltage vdd 4.75 5 5.25 v r ef erence voltage vref 4 4.5 4.6 v photodiode voltage vpd - vref - v gain selection terminal voltage high gain vgain vdd - 0.25 vdd vdd + 0.25 v low gain 0 - 0.4 v master/slave selection voltage high level * 3 vms vdd - 0.25 vdd vdd + 0.25 v low level * 4 0 - 0.4 v clock pulse voltage high level v(clk) 3.3 vdd vdd + 0.25 v low level 0 - 0.4 v reset pulse voltage high level v(reset) 3.3 vdd vdd + 0.25 v low level 0 - 0.4 v external start pulse voltage high level v(extsp) vdd - 0.25 vdd vdd + 0.25 v low level 0 - 0.4 v * 3: parallel * 4: serial at 2nd or later stages parameter symbol min. typ. max. unit clock pulse frequency * 5 f(clk) 40 - 2000 khz line rate s8865-64g lr - 7339 - lines/s s8865-128g, s8866-128-02g - 3784 - s8865-256g - 1922 - s8866-64g-02 - 6838 - output impedance zo - 3 - k power consumption s8865-64g, s8866-64g-02 p - 100 - mw s8865-128g, s8866-128g-02 - 180 - s8865-256g - 360 - charge amp feedback capacitance high gain cf - 0.5 - pf low gain - 1 - * 5: video data rate is 1/4 of clock pulse frequency f(clk).
photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 3 electrical and optical characteristics [ta=25 c, vdd=5 v, v(clk)=v(reset)=5 v, vgain=5 v (high gain), 0 v (low gain)] parameter symbol s8866-64g-02 s8866-128g-02 unit min. typ. max. min. typ. max. peak sensitivity wavelength * 6 p - 720 - - 720 - nm dark output voltage * 7 high gain vd - 0.01 0.2 - 0.01 0.2 mv low gain - 0.005 0.1 - 0.005 0.1 saturation output voltage vsat 3 3.5 - 3 3.5 - v saturation exposure * 6 * 8 high gain esat - 0.2 0.25 - 0.8 1.0 mlx s low gain - 0.4 0.5 - 1.6 2.0 photo sensitivity * 6 * 8 high gain s 14400 18000 - 3520 4400 - v/lx s low gain 7200 9000 - 1760 2200 - photo response non- uniformity * 9 3 channels from both ends prnu - - -25, +10 - - -35, +10 % all channels excluding 3 channels from both ends - - 10 - - 10 noise * 10 high gain n - 2.0 3.0 - 1.3 2.0 mvrms low gain - 1.1 1.7 - 0.7 1.1 output offset voltage * 11 vos - vref - - vref - v *6: measured without phosphor sheet * 7: integration time ts=1 ms *8: measured with a 2856 k tungsten lamp * 9: when the photodiode array is exposed to uniform light which is 50% of the saturation exposure, the photo response non-uinifo rmity (prnu) is de t ned as follows: prnu = x/x 100 [%] x: average output of all elements, x: difference between x and the maximum or minimum output, whichever is larger. * 10: measured with a video data rate of 50 khz and ts=1 ms in dark state * 11: video output is negative-going output with respect to the output offset voltage. parameter symbol s8865-64g s8865-128g s8865-256g unit min. typ. max. min. typ. max. min. typ. max. peak sensitivity wavelength * 6 p - 720 - - 720 - - 720 - nm dark output voltage * 7 high gain vd - 0.01 0.2 - 0.01 0.2 - 0.01 0.2 mv low gain - 0.005 0.1 - 0.005 0.1 - 0.005 0.1 saturation output voltage vsat 3.0 3.5 - 3.0 3.5 - 3.0 3.5 - v satur ation exposure * 6 * 8 high gain esat - 0.8 1.0 - 2.4 3.0 - 15 19 mlx s low gain - 1.6 2.0 - 4.8 6.0 - 30 37.5 photo sensitivity * 6 * 8 high gain s 3520 4400 - 1200 1500 - 200 250 - v/lx s low gain 1760 2200 - 600 750 - 100 125 - photo response non- unif ormit y * 9 3 channels from both ends prnu -- -35, +10 -- -55, +10 -- -70, +10 % all channels excluding 3 channels from both ends - - 10 - - 10 - - 10 noise * 10 high gain n - 1.3 2.0 - 1.0 1.5 - 0.8 1.2 mv rms low gain - 0.7 1.1 - 0.6 0.9 - 0.5 0.75 output offset voltage * 11 vos - vref - - vref - - vref - v s8865-64g/-128g/-256g s8866-64g-02/-128g-02
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photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 5 timing chart kmpdc0289ec parameter symbol min. typ. max. unit clock pulse width tpw(clk) 500 - 25000 ns clock pulse rise/f all times tr(clk), tf(clk) 0 20 30 ns reset pulse width 1 tpw(reset1) 21 - - clk reset pulse width 2 tpw(reset2) 20 - - clk reset pulse rise/fall times tr(reset), tf(reset) 0 20 30 ns clock pulse-reset pulse timing 1 t1 -20 0 20 ns clock pulse-reset pulse timing 2 t2 -20 0 20 ns 1. the internal timing circuit starts operation at the falling edge of clk immediately after a reset pulse goes low. 2. when the falling edge of each clk is counted as ?1 clock?, the video signal of the 1st channel appears between ?18.5 clocks and 20.5 clocks?. subsequent video signals appear every 4 clocks. 3. the trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. the rising edge of each trigger pulse is the recommended timing for data acquisition. 4. signal charge integration time equals the high period of a reset pulse. however, the charge integration does not start at th e rise of a reset pulse but starts at the 8th clock after the rise of the reset pulse and ends at the 8th clock after the fall of the reset pulse. after the reset pulse next changes from high to low, signals integrated within this period are sequentially read out as time-se ries signals by the shift register operation. the rise and fall of a reset pulse must be synchronized with the rise of a clk pulse, but the rise of a reset pulse must be set outside the video output period. one cycle of reset pulses cannot be set shorter than the tim e equal to ?16.5 + 4 n (number of elements)? clocks. 5. the video signal after an eos signal output becomes a high impedance state, and the video output will be inde nite. s8865-64g/-128g/-256g, s8866-128g-02 kmpd 1 2 3 16 1 2 3 17 video output period clk reset video trig eos tpw(reset2) 18 19 20 21 22 23 24 25 26 27 28 29 30 123n - 1n 8 clocks integration time 8 clocks tpw(reset1) tf(clk) tf(reset) tpw(clk) t1 t2 tpw(reset1) tpw(reset2) tr(clk) tr(reset)
photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 6 kmpdc0278ec parameter symbol min. typ. max. unit clock pulse width tpw (clk1), tpw (clk2) 500 - 12500 ns clock pulse rise/f all times tr (clk), tf (clk) 0 20 30 ns reset pulse width 1 tpw (reset1) 21 - - clk reset pulse width 2 tpw (reset2) 20 - - clk reset pulse rise/fall times tr (reset), tf (reset) 0 20 30 ns clock pulse-reset pulse timing 1 t1 -20 0 20 ns clock pulse-reset pulse timing 2 t2 -20 0 20 ns 1. the internal timing circuit starts operation at the falling edge of clk immediately after a reset pulse goes low. 2. when the falling edge of each clk is counted as ?1 clock?, the video signal of the 1st channel appears between ?18.5 clocks and 20.5 clocks?. subsequent video signals appear every 4 clocks. 3. to obtain video signals, extend the high period 3 clocks from the falling edge of clk immediately after the reset pulse goes low, to a 20 clock period. 4. the trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. the rising edge of each trigger pulse is the recommended timing for data acquisition. 5. signal charge integration time equals the high period of a reset pulse. however, the charge integration does not start at th e rise of a reset pulse but starts at the 8th clock after the rise of the reset pulse and ends at the 8th clock after the fall of the reset pulse. after the reset pulse next changes from high to low, signals integrated within this period are sequentially read out as time- series signals by the shift register operation. the rise and fall of a reset pulse must be synchronized with the rise of a clk pulse, but the rise of a reset pulse must be set outside the video output period. one cycle of reset pulses cannot be set shorter than the time equal to ?36.5 + 4 n (number of elements)? clocks. 6. the video signal after an eos signal output becomes a high impedance state, and the video output will be inde nite. s8866-64g-02 kmpdc0 1 2 3 16 1 2 3 4 5 17 video output period clk reset video trig eos tpw(reset2) 18 19 20 21 22 23 24 25 26 27 28 29 30 123n - 1n 8 clocks 8 clocks integration time tpw(reset1) 20 clocks tf(clk) tf(reset) tpw(clk) t1 t2 tpw(reset1) tpw(reset2) tr(clk) tr(reset)
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photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 10 pin connection pin no. symbol name note 1 reset reset pulse pulse input 2 clk clock pulse pulse input 3 trig trigger pulse positive-going pulse output 4 extsp external start pulse pulse input 5 vms master/slave selection supply voltage voltage input 6 vdd supply voltage voltage input 7 gnd ground 8 eos end of scan negative-going pulse output 9 video video output negative-going output with respect to vref 10 vref reference voltage voltage input 11 vgain gain selection terminal voltage voltage input 12 vpd photodiode voltage voltage input pin no. cmos1 pin no. cmos2 name note 1 vpd 14 vpd photodiode voltage voltage input 2 reset 15 reset reset pulse pulse input 3 clk 16 clk clock pulse pulse input 4 trig 17 trig trigger pulse positive-going pulse output 5 extsp 18 extsp external start pulse pulse input 6 vms 19 vms master/slave selection supply voltage voltage input 7 vdd 20 vdd supply voltage voltage input 8 gnd 21 gnd ground 9 eos 22 eos end of scan negative-going pulse output 10 video 23 video video output negative-going output with respect to vref 11 vref 24 vref reference voltage voltage input 12 vg 25 vg gain selection terminal voltage voltage input 13 vpd 26 vpd photodiode voltage voltage input s8865-64g/-128g, s8866-64g-02/-128g-02 s8865-256g
photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 11 setting for each readout method set to a in the table below in most cases. to serially read out signals from two or more sensors linearly connected, set the 1st sensor to a and the 2nd or later sensors to b. the clk and reset pulses should be shared with each sensor and the video output terminal of each sensor connected together. setting readout method vms extsp a all stages of parallel readout, serial readout at 1st sensor vdd vdd b serial readout at 2nd and later sensors gnd preceding sensor eos should be input gain selection terminal voltage setting vdd: high gain (cf=0.5 pf) gnd: low gain (cf=1 pf) [figure 1] connection example (parallel readout) ! ! "#$ % & ' ( ) * + , - ( kmpdc0288eb s8866-64g/-128g, s8866-64g-02/-128g-02
photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 12 readout circuit check that pulse signals meet the required pulse conditions before supplying them to the input terminals. video output should be ampli ed by an operational ampli er that is connected close to the sensor. signals of channels 1 through 126 are output from cmos1, while signals of channels 129 through 256 are output from cmos2. the f ol- lowing two readout methods are available. (1) serial readout method cmos1 and cmos2 are connected in serial and the signals of channels 1 thr ough 256 are sequentially read out from one output lin e. set cmos1 as in ?a? in the table below, and set cmos2 as in ?b?. cmos1 and cmos2 should be connected to the same clk and reset lines, and their video output terminals to one line. (2) parallel readout method 128 channel signals are output in parallel respectively from the output lines of cmos1 and cmos2. set both cmos1 and cmos2 as i n ?a? in the table below. setting vms extsp a vdd vdd b gnd preceding sensor eos should be input s8865-256g [figure 2] connection

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photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 13 procautions for use (1) the signal processing ic chip is protected against static electricity. however, in order to prevent possible damage to the ic chip, take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. also protect the ic chip from su rge voltages from peripheral equipment. (2) gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. the signal processing ic chip, wire bonding section and photodiode array chip are covered with resin for protection. however, never touch these portions. excessive force, if applied, may break the wires or cause malfunction. blow air to remove dust or debris if it gets on the protective resin. never wash them with solvent. signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing ic chip or photodiode array chip is nicked. (3) the photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enc losure or case. when installing the photodiode array on a board, be careful not to cause the board to warp. (4) the characteristics of the signal processing ic chip deteriorate if exposed to x-rays. so use a lead shield which is at least 1 mm larger all around than the signal processing ic chip. the 1 mm margin may not be suf cient depending on the incident angle of x-rays. provide an even larger shield as long as it does not cover the photodiode active area. since the optimal shield thickne ss depends on the operating conditions, calculate it by taking the attenuation coef cient of lead into account. (5) the sensitivity of the photodiode array chip decreases if continuously exposed to x-rays. the extent of this sensitivity de crease differs depending on the x-ray irradiation conditions, so before beginning measurement, check how much the sensitivity decrease s under the x-ray irradiation conditions to be used. driver circuit c9118 series (sold separately) the cmos driver circuit is designed for the s8865-64g/-128g and s8866-128g-02 photodiode arrays with ampli er. the c9118 series operates a photodiode by just inputting two signals (m-clk and m-reset) and a signal +5 v supply. the c9118 is intended for single use or parallel connections, while the c9118-01 is suitable for cascade connections. features single power supply (+5 v) operation operation with two input signals (m-clk and m-reset) compact: 46 56 5.2 t mm
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photodiode arrays with ampli er s8865-64g/-128g/-256g, s8866-64g-02/-128g-02 cat. no. kmpd1105e06 feb. 2014 dn 15 www.hamamatsu.com hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184 u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 8152-375-0, fax: (49) 8152-265-8 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, telephone: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, united kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: thorshamnsgatan 35 16440 kista, sweden, telephone: (46) 8-509-031-00, fax: (46) 8- 509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1 int. 6, 20020 arese, (milano), italy, telephone: (39) 02-935-81-733, fax: (39) 02-935-81-741 china: hamamatsu photonics (china) co., ltd.: 1201 tower b, jiaming center, no.27 dongsanhuan beilu, chaoyang district, beijing 100020, china, telephone: (86) 10-6586-6006, fax: (86) 10-6586-2866 product specifications are subject to change without prior notice due to improvements or other reasons. this document has been carefully prepared and the information contained is believed to be accurate. in rare cases, however, there may be inaccuracies such as text errors. before using these products, always contact us for the delivery specification sheet to check the latest specifications. t ype numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(x)" which means preliminary specifications or a suffix "(z)" which means developmental specifications. t he product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. however, even if within the warranty period we accept absolutely no liability for any loss caused by natural d isasters or improper product use. copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. information described in this material is current as of february, 2014. cascade readout example (c9118-01) simultaneous integration/serial output (simplifies external processing circuit)

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